1. Technical Field
The present invention relates generally to bipolar transistors, and more particularly, to a bipolar transistor structure with a self-aligned raised extrinsic base and method of fabricating the same.
2. Related Art
Self-aligned bipolar transistors with raised extrinsic base are the focus of integrated circuits fabricated for high performance mixed signal applications. Producing bipolar transistors for high speed applications requires improvements to the NPN junction to improve unit current gain frequency (fT) and maximum oscillation frequency (fMAX). fT is inversely proportional to base transit time (tb) (i.e., 1/tb) and collector-base capacitance (Ccb) (i.e., 1/Ccb). One approach to reduce transit time is to eliminate base widening due to thermal enhanced diffusion (TED) effects on the extrinsic base and loss of intrinsic base definition caused by the lateral diffusion of dopants during implantation of the extrinsic base. A deposited, raised extrinsic base eliminates implant damage in the intrinsic base region and therefore does not precipitate base widening during formation. A more important RF design parameter is fMAX, which is proportional to (fT/(Rb*Ccb))0.5. fMAX benefits from improved fT and collector-base capacitance (Ccb), but also requires reducing base resistance (Rb). There are several methods to improve Rb, an important aspect of which is emitter-base alignment. A fully self-aligned raised extrinsic base method will improve fT and fMAX of a bipolar transistor. Current approaches to achieve these improvements increase process complexity in order to maintain the extrinsic base self-aligned to the emitter, or employ a non-self aligned (NSA) structure in favor of a more simple process.
An approach for self-aligned with raised extrinsic base fabrication is disclosed by Chantre et al. in U.S. Pat. No. 6,472,262 B2. However, the Chantre et al. process results in less lateral control and higher base resistance due to continuous oxide layer 20, which leads to not only increased Rb but also poorer Rb control. Etch selectivity of silicon-germanium to silicon is required.
Another approach is disclosed in Ahlgren in US Publication No. 2003-0064555A1. However, this process is complex.
Another challenge to improving ICs fabricated for high performance mixed signal applications is that performance of self-aligned bipolar transistors with extrinsic base degrades as the emitter dimension is reduced due to loss of intrinsic base definition caused by the lateral diffusion of dopants. To maintain high electrical performance, bipolar transistors must have a polysilicon extrinsic base layer self-aligned to the emitter on top of the epitaxially grown intrinsic silicon germanium (SiGe) base. That is, a raised extrinsic base must exist. Transistors fabricated using this approach have demonstrated the highest unit current gain frequency (fT) (also referred to as cutoff frequency) and the maximum oscillation frequency (FMAX) to date.
A number of approaches of forming a self-aligned bipolar transistor with raised polysilicon extrinsic base have been implemented. In one approach, chemical mechanical polishing (CMP) is used to planarize the extrinsic base polysilicon over a pre-defined sacrificial emitter pedestal, as disclosed by Bronner et al. in U.S. Pat. No. 5,128,271 and Kovacic et al. in U.S. Pat. No. 6,346,453. In this approach, an extrinsic base of area A and depth D is constructed to have a low aspect ratio (D/A<<1), which can lead to a significant difference in the extrinsic base layer thickness between the small and large devices, and isolated and nested devices, due to dishing caused by the CMP.
In another approach, an intrinsic base is grown using selective epitaxy inside an emitter opening and an undercut is formed under the extrinsic base polysilicon, as disclosed by Imai in U.S. Pat. Nos. 5,494,836 and 5,506,427, Sato in U.S. Pat. No. 5,599,723 and Oda et al. in U.S. Pat. No. 5,962,880. In this approach, the self-alignment of the extrinsic base is achieved with the epitaxial growth inside the undercut. Unfortunately, special techniques are required to ensure a good link-up contact between the intrinsic base and the extrinsic base.
In the parent application, the approach implemented an epitaxial growth to link the extrinsic base to an intrinsic base that is grown non-selectively. One drawback of this approach is that the epitaxial growth to form the link-up also forms a silicon layer over the emitter cap layer at the bottom of the opening. As a result, the silicon layer needs to be oxidized to consume the excess silicon. The oxidation of the excess silicon layer is detrimental in a number of ways. First, it causes widening of the base profile, which reduces fT. Second, it causes non-uniform emitter cap thickness because it is difficult to control the depth of penetration of the oxidation. This situation results in widespread transistor current gain, Icollector/Ibase. Finally, it causes stress at the bottom corners of the emitter/base junction.
Other approaches to achieve these improvements increase process complexity in order to maintain the extrinsic base self-aligned to the emitter, or employ a non-self aligned (NSA) structure in favor of a more simple process.
In view of the foregoing, there is a need in the art for a method of fabricating a self-aligned bipolar transistor structure that does not suffer from the problems of the related art.